1. Field of the Invention
The present invention relates to a method of estimating a range of pessimistic errors in prediction calculations of yields of the production of LSIs by using statistical static timing analysis (SSTA).
2. Description of the Related Art
Generally in SSTA, timing is checked in units of paths that include all the gates and nets on all the paths connecting one sequential circuit with another, the sequential circuits themselves serving as the source and sink points, and distributions of the check values are calculated. A formula used for the timing check includes delay distributions between sequential circuits of source points and sink points, and delay distributions of clock paths that provide clock signals to the sequential circuits of the source points and the sink points. This means that the timing delay distribution on one path is calculated by using timing delay distributions that are input as timing distributions of respective sequential circuits.
It is assumed that when a timing check with a sequential circuit i which operates as the source point and a sequential circuit j which operates as the sink point is considered, the distribution of the check values is referred to as check value distribution ij, and a set of all the nets and gates on the LSIs related to the delay distributions between the sequential circuits of the source points and the sink points included in the timing check formula used for obtaining the check value distribution ij is referred to as a delay element set ij. This means that the delay element set ij includes all the nets and gates on at least one of the paths connecting the sequential circuits i and j.
When predicted values of yields of the production of LSIs are calculated, the check value distributions of all the LSIs are calculated, and a statistical max calculation is performed on the calculated check value distributions. The statistical max calculation is a multiplication of cumulative distributions. When the statistical max calculation is explained by using the example of two cumulative distribution functions (CDFs) C1 and C2, the result of the statistical max calculation on C1 and C2 can be expressed by the formula below.C(t)=C1(t)×C2(t) (t is a variable)
FIG. 1 shows an example of a result of the statistical max calculation on the cumulative distribution functions.
In FIG. 1, the result of the statistical max calculation on the cumulative distribution function C1 and the cumulative distribution function C2 is shown as the line denoted by the cumulative distribution function C1×C2. The cumulative distribution function C1×C2 presents a lower yield than the cumulative distribution function C1 or C2, which indicates that when the statistical max calculation is performed on the cumulative distribution functions, the resultant cumulative distribution function presents a yield value lower than that of the distribution before the statistical max calculation.
In the prediction calculations of yields of the production of LSIs, cumulative distribution functions are calculated on check value distributions of all the paths, and the statistical max calculations are performed on them. Then, one distribution is obtained for one LSI. The value of the point corresponding to the target (spec) frequency of the LSI on the distribution is dealt with as the yield at that target frequency.
Generally, a net or a gate can be one of the elements in a delay element set. In other words, one gate can be a gate on a path starting from a sequential circuit i to a sequential circuit j, and also a gate on a path starting from a sequential circuit l to a sequential circuit m.
The delaying behavior of one and the same gate or net on one LSI (delay values, delay value distributions) is determined by temperature, voltage, and production conditions; accordingly, when the timing check value distribution ij of the delay element set ij including a gate or a net and the timing check value distribution lm of another delay element set lm including the gate or the net are calculated, that gate or net experiences the same delaying/physical behavior. Accordingly, the prediction calculation of yields is desired to reflect this condition. Note that the function obtained by integrating the timing check value distribution is the cumulative distribution function.
However, in the conventional and commonly employed SSTA, it is difficult to subordinately deal with delay distributions of the gates and nets included in a plurality of delay element sets such as those described above in calculations, and actually the delay distributions of the nets and gates are independently dealt with as methods that can be used for designing LSIs (in other words, the process is executed in which one gate is assumed to belong to the delay element set ij in a calculation of a timing check value distribution, also the same gate is assumed to belong to the delay element set lm in a calculation of another timing check value distribution, and these timing check value distributions are separately calculated; thereafter the cumulative distribution functions are obtained by performing the statistical max calculation, which is a method that allows phenomena that cannot actually occur). Accordingly, it is known that the yield finally calculated out by using the SSTA involves errors in the pessimistic direction (in the direction in which the yields are reduced) more than the yield calculated in a manner such that the common parts over gates and nets are subordinately dealt with in accordance with the actual physical properties in calculation. In other words, in the commonly employed SSTA, when the timing check value distributions of the common delay elements over two paths in an LSI are obtained, the elements are dealt with as separate elements, and the prediction calculation of the yield of one LSI is performed by performing the statistical max calculations on cumulative distribution functions on the basis of the timing check value distributions that have been respectively obtained. As is explained in the above descriptions, in the statistical max calculation, the more cumulative distribution functions to be calculated there are, the lower the prediction of the yield tends to be. However, when performing the statistical max calculation on the cumulative distribution functions that have been separately obtained on the assumption that the same element belongs to different paths (delay element sets), the result is obtained in which the delay characteristic of the element is duplicately taken into consideration. In this SSTA, a predicted value that is more pessimistic than the actual yield is obtained.
In order to perform the accurate prediction of yields, it is necessary to avoid the above calculations, which means that the prediction calculations of yields have to be performed by using the Monte Carlo method. However, the Monte Carlo method requires a very large number of sample points, and commonly and currently available computers cannot calculate out results, within the limit of realistic time spans and calculation amounts, of the prediction calculations of yields of LSIs that include many delay elements.
The systems that perform the conventional timing analysis and the like are disclosed in Patent Documents 1 and 2.
Patent Document 1
Japanese Patent Application Publication No. 7-13974
Patent Document 2
Japanese Patent Application Publication No. 2005-92885
In view of the above problems, realization of accurate prediction calculations of yields of LSIs using statistical static timing analysis is desired.